Voltage-controlled oscillator having short synchronous pull-in time

ABSTRACT

A voltage-controlled oscillator comprises a control terminal applied to a control voltage, first and second output terminals, first and second ring oscillators, first and second output buffer circuits and a latch circuit. Each of the first and second ring oscillators includes an odd number of inverting amplifier circuits connected in series and a transfer gate circuit connected between the inverting amplifier circuits and a resistive element connected in parallel to the transfer transistor. The transfer gate circuit includes a transfer transistor connected between the inverting amplifier circuits. The transfer gate circuit has a control terminal connected to the control terminal. Each of the first and second output buffer circuits has an input connected to the first or second ring oscillator and an output connected to the first or second output terminal. The latch circuit is connected to the first and second ring oscillators. The latch circuit controls the first and second ring oscillators so as to output complement oscillation signals.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a voltage-controlled oscillator(hereinafter called “VCO”) whose oscillation frequency can be controlledaccording to a control voltage.

[0003] 2. Description of the Related Art

[0004] A conventional VCO has ring oscillators each comprised of aplurality of inverters and a transfer gate (hereinafter called “TG”)connected in ring form. An oscillating operation of the VCO is performedat a frequency corresponding to a loop delay time of each ringoscillator. The loop delay time corresponds to the sum of delay times ofthe inverters and a delay time of the TG. The delay time of each TGchanges according to a control voltage supplied to a control terminal.Namely, when the control voltage is lowered, the TG increases in channelresistance to thereby make an increase in delay time, whereby anoscillation frequency is reduced. When the control voltage is raised inreverse, the TG is reduced in channel resistance to thereby make adecrease in delay time, whereby an oscillation frequency increases. Itis thus possible to control the oscillation frequency over a relativelywide range.

[0005] However, the conventional VCO has the following problems.

[0006] One of them is that since the frequency to be fixed is alreadydetermined when, for example, the VCO is used to configure aphase-locked loop (hereinafter called “PLL”), a synchronous pull-in timeat phase synchronization becomes long under the influence of a widefrequency control range that would be a characteristic of theconventional VCO.

[0007] Further, another is that due to insertion losses and gatecapacitance of field-effect transistors (hereinafter called “FETs”)constituting each TG, a delay time increases and hence the upper limitof an oscillation frequency is restricted.

SUMMARY OF THE INVENTION

[0008] An object of the present invention is to provide a VCO whichobtains a high oscillation frequency and is short in synchronous pull-intime when it is used in PLL.

[0009] In order to solve the above problems, the present inventionprovides a VCO comprising inverting amplifier circuits each comprised ofan odd number of inverting amplifiers connected in tandem, feedbacktransistors which are connected between the outputs and inputs of theinverting amplifier circuits and whose conducting states are controlledaccording to a control voltage supplied to control electrodes thereof,respectively, and feedback resistors each connected in parallel with thefeedback transistor between the output and input of the invertingamplifier circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] While the specification concludes with claims particularlypointing out and distinctly claiming the subject matter which isregarded as the invention, it is believed that the invention, theobjects and features of the invention and further objects, features andadvantages thereof will be better understood from the followingdescription taken in connection with the accompanying drawings in which:

[0011]FIG. 1 is a circuit diagram of a VCO showing a first embodiment ofthe present invention;

[0012]FIG. 2 is a conceptual diagram showing a frequency response of theVCO shown in FIG. 1;

[0013]FIG. 3 is a circuit diagram of a VCO showing a second embodimentof the present invention;

[0014]FIG. 4 is a conceptual diagram illustrating a characteristicresponse of the VCO shown in FIG. 3; and

[0015]FIG. 5 is a circuit diagram of a VCO showing a third embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Preferred embodiments of the present invention will hereinafterbe described in detail with reference to the accompanying drawings.

[0017]FIG. 1 is a circuit diagram of a VCO showing a first embodiment ofthe present invention.

[0018] This type of VCO is one of a ring oscillation type for generatinga clock signal of a logical circuit, for example, and has an invertingamplifier circuit which comprises an odd number of (e.g., three)inverting amplifiers (e.g., inverters) 11 through 13 connected intandem. The output of the inverter 13 is electrically connected to theinput of the inverter 11 through a TG 14 wherein feedback transistors(e.g., a depletion type field-effect transistor (hereinafter called“DFET”) 14 a and an enhancement type field-effect transistor (hereaftercalled “EFET”) 14 b) are connected in parallel. Further, a feedbackresistor 17 s electrically connected in parallel with the TG 14. Anoutput buffer 15 comprised of cascade-connected inverters 15 a through15 c is electrically connected to the output of the inverter 12. Theoutput of the output buffer 15 is electrically connected to an outputterminal 16.

[0019] The VCO has three cascade-connected inverters 21 through 23. Theoutput of the inverter 23 is electrically connected to the input of theinverter 21 through a TG 24 wherein a DFET 24 a and an EFET 24 b areconnected in parallel. Further, a feedback resistor 27 is electricallyconnected in parallel with the TG 24. An output buffer 25 comprised ofcascade-connected inverters 25 a through 25 c is electrically connectedto the output of the inverter 22. The output of the output buffer 25 iselectrically connected to an output terminal 26.

[0020] Control electrodes (e.g., gates) of the DFETs 14 a and 24 a andthe EFETs 14 b and 24 b constituting the TGs 14 and 24 respectively areelectrically connected to a control terminal 31 supplied with a controlvoltage CLT. Further, the outputs of the TGs 14 and 24 are connected toeach other by a latch 32 comprised of two inverters 32 a and 32 b.Namely, the input of the inverter 32 a is electrically connected to theoutput of the TG 14, and the output of the inverter 32 a is electricallyconnected to the output of the TG 24. Further, the input of the inverter32 b is electrically connected to the output of the TG 24, and theoutput of the inverter 32 b is electrically connected to the output ofthe TG 14. The latch 32 always controls a signal outputted from a ringoscillator comprised of the inverters 11 through 13 and the TG 14 and asignal outputted from a ring oscillator comprised of the inverters 21through 23 and the TG 24 so that ring oscillators output complementaryoscillation signals. In the present embodiment, GaAs MESFETs are used ascircuit elements to perform a high-speed operation.

[0021] The operation of the VCO will next be described.

[0022] In the VCO, the ring oscillator comprised of the inverters 11through 13, the TG 14 and the resistor 17 performs an oscillatingoperation at a frequency corresponding to its loop delay time. The loopdelay time corresponds to the sum of delay times produced in theinverters 11 through 13, and a delay time developed in a parallelcircuit comprised of the TG 14 and the resistor 17. Of the total delaytime, the delay time of the TG 14 changes according to the controlvoltage CLT applied to the control terminal 31. Namely, when the controlvoltage CLT is lowered, the TG 14 increases in channel resistance andthe combined resistance of the TG 14 and the resistor 17 increases, thusresulting in an increase in delay time and a reduction in oscillationfrequency. When the control voltage CLT increases in reverse, thechannel resistance of the TG 14 becomes small and the combinedresistance of the TG 14 and the resistor 17 decreases, thus resulting ina decrease in delay time and an increase in oscillation frequency.

[0023] Even in the case of the ring oscillator comprised of theinverters 21 through 23 and the resistor 27, the oscillation frequencyis controlled according to the control voltage CLT in a manner similarto the above.

[0024] These two ring oscillators are connected to each other throughthe latch 32 by which their output signals are controlled so as tooutput inverted oscillation signals. A part of the signal outputted fromthe inverter 12 is outputted as an oscillation signal QY from the outputterminal 16 via the output buffer 15. On the other hand, a part of thesignal outputted from the inverter 22 is outputted from the outputterminal 26 via the output buffer 25 as an oscillation signal QNopposite in polarity to the oscillation signal QY.

[0025] The output signals of the inverting amplifier circuits eachcomprised of the odd number of inverting amplifiers are respectively fedback to the inputs of the inverting amplifier circuits through thefeedback transistors whose conducting states are controlled according tothe control voltage, and the feedback resistors connected in paralleltherewith to perform the oscillating operations. Since, at this time,the loop delay times differ from each other according to the conductingstates of the feedback transistors, the transistors are controlled bythe control voltage so that the oscillation frequencies of the VCO canbe controlled. The suitable setting of the value of the resistorparallel-connected to each transistor makes it possible to bring avariable range of the oscillation frequency to a desired value.

[0026]FIG. 2 is a conceptual diagram showing a frequency response of theVCO shown in FIG. 1. A horizontal axis thereof indicates a controlvoltage CLT, and a vertical axis thereof indicates an oscillationfrequency. The relationship between the control voltage CLT and theoscillation frequency is conceptually shown in solid line in thedrawing. Incidentally, a broken line in FIG. 2 indicates a frequencyresponse of a conventional VCO, which has been described for comparison.

[0027] As shown in FIG. 2, when the control voltage CLT is high, the TGs14 and 24 are reduced in channel resistance, and the influence of theresistors 17 and 27 connected in parallel with the TGs 14 and 24 islessened. Thus, the difference between the oscillation frequencies ofthe conventional VCO and the VCO shown in FIG. 1 is small.

[0028] On the other hand, when the control voltage CLT is lowered, thechannel resistances of the TG 14 and 24 increase and hence the resistors17 and 27 connected in parallel with the TGs 14 and 24 becomepredominant. Thus, even if the control voltage CLT is reduced, thecombined resistances of the TGs 14 and 24 and the resistors 17 and 27are not so high and hence a decrease in the oscillation frequency islow. On the other hand, since the resistors 17 and 27 are not connectedin parallel with the TGs 14 and 24 in the conventional VCO, theoscillation frequency is greatly reduced according to the increase inthe channel resistance of each of the TGs 14 and 24 as indicated by thebroken line in FIG. 2.

[0029] Since the resistors 17 and 27 are respectively connected inparallel with the TGs 14 and 24 in the VCO according to the firstembodiment as described above, the variable range of each of thecombined resistances of these TGs 14 and 24 and resistors 17 and 27 canbe narrowed. Thus, an advantage is brought about in that the suitableselection of the values of the resistors 17 and 27 allows the setting ofa desired oscillation frequency control ranges and a synchronous pull-intime can be shortened when PLL is used in the VCO.

[0030]FIG. 3 is a circuit diagram of a VCO showing a second embodimentof the present invention. Elements of structure common to the elementsshown in FIG. 1 are respectively identified by the common referencenumerals.

[0031] In a manner similar to the VCO shown in FIG. 1, the present VCOis one of a ring oscillation type for generating a clock signal of alogical circuit, for example, and has three inverters 11 through 13connected in ring form. The output of the inverter 13 is electricallyconnected to the input of the inverter 11 and connected to the drain ofa load FET 19 through a load resistor 18. The source of the FET 19 iselectrically connected to a common potential (e.g., ground potential)GND. The gate of the FET 19 is electrically connected to a controlterminal 31 and supplied with a control voltage CLT. The output of theinverter 12 is electrically connected to an output terminal 16 throughan output buffer 15.

[0032] Similarly, the VCO has three inverters 21 through 23 connected inring form. The output of the inverter 23 is electrically connected to aground potential GND through a resistor 28 and an FET 29 connected inseries. The gate of the FET 29 is electrically connected to the controlterminal 31 and supplied with the control voltage CLT. The output of theinverter 22 is electrically connected to an output terminal 26 throughan output buffer 25. Further, the outputs of the inverters 13 and 23 areelectrically connected to each other by a latch 32.

[0033] The operation of the present embodiment will next be described.

[0034] The inverters 11 through 13 and the inverters 21 through 23connected in ring form are respectively operated as three-stage ringoscillators. The latch 32 antiphase-drives the two ring oscillators.Thus, oscillation signals QY and QN identical in frequency and oppositein polarity to each other are outputted from the output terminals 16 and26.

[0035] At this time, a series circuit comprised of the resistor 18 andthe FET 19 connected between the output of the inverter 13 and theground potential GND, and a series circuit comprised of the resistor 28and the FET 29 connected between the output of the inverter 23 and theground potential GND respectively operate as loads of the ringoscillators.

[0036] A ring oscillator comprised of an odd number of invertingamplifiers connected in ring form performs an oscillating operation at afrequency corresponding to its loop delay time. At this time, anoscillation frequency changes according to the load on each loadtransistor connected between the output of each inverting amplifier anda power source or supply or a common potential. Thus, a control voltageapplied to a control electrode of the load transistor can be changed soas to control the magnitude of the load and an oscillation frequency.

[0037]FIG. 4 is a conceptual diagram showing a frequency response of theVCO shown in FIG. 3. A horizontal axis thereof indicates a controlvoltage CLT, and a vertical axis thereof indicates an oscillationfrequency. The relationship between the control voltage CLT and theoscillation frequency is conceptually shown in solid line in thedrawing. Incidentally, a dashed line in FIG. 4 indicates a frequencyresponse obtained when the resistance values R of the resistors 18 and28 are set to zero.

[0038] As shown in FIG. 4, when the control voltage CLT is low, thechannel resistances of the FETs 19 and 29 are almost assumed to beinfinite and hence the loads on the inverters 13 and 23 are virtuallynonexistent. Thus, the highest frequency substantially corresponding toa loop delay time of the inverters 11 through 13 is obtained as theoscillation frequency. Namely, when the control voltage CLT is low, thevalues of the channel resistances of the FETs 19 and 29 becomepredominant as compared with the resistance values of the resistors 18and 28. Thus, the difference developed between the oscillationfrequencies at the low control voltage CLT by the resistance values ofthe resistors 18 and 28 is small.

[0039] On the other hand, when the control voltage CLT increases, thechannel resistances of the FETs 19 and 29 become low and-hence the loadson the inverters 13 and 23 increase, whereby the oscillation frequenciesare reduced. Since the resistors 18 and 28 are respectively connected inseries with the FETs 19 and 29, the values of the resistors 18 and 28become predominant in this case. Namely, when the control voltage CLT ishigh, an increase in load becomes great as the values of the resistors18 and 28 decrease, whereby the proportion of a reduction in oscillationfrequency becomes large.

[0040] In the VCO according to the second embodiment as described above,the series circuit comprised of the resistors 18 and 19 and the seriescircuit comprised of the resistors 28 and the FET 29 are connectedbetween the outputs of the inverters 13 and 23 respectively constitutingthe ring oscillators and the ground potential GND, as the loads.

[0041] Thus, the control of the channel resistances of the FETs 19 and29 by the control voltage CLT makes it possible to change the loads ofthe ring oscillators from nearly zero to a predetermined value.Accordingly, an advantage is brought about in that a desired oscillationfrequency control range can be set by suitably selecting the values ofthe resistors 18 and 28.

[0042] A further advantage is brought about in that since the load ofeach ring oscillator can be set to nearly zero by lowering the controlvoltage CLT, a high oscillation frequency is obtained without loweringthe oscillatable highest frequency.

[0043]FIG. 5 is a circuit diagram of a VCO showing a third embodiment ofthe present invention. Elements of structure common to the elementsshown in FIGS. 1 and 3 are respectively identified by the commonreference numerals.

[0044] The present VCO is a modification of the VCO shown in FIG. 3 andhas a combined configuration of the VCOs shown in FIGS. 1 and 3. Namely,the VCO has a ring oscillator wherein three inverters 11 through 13 anda TG 14 are connected in ring form, and a ring oscillator wherein threeinverters 21 through 23 and a TG 24 are connected in ring form. Further,a resistor 18 and an FET 19 connected in series are electricallyconnected between the output of the inverter 13 and a ground potentialGND. A resistor 28 and an FET 29 connected in series are electricallyconnected between the output of the inverter 23 and the ground potentialGND. The gates of the FETs 19 and 29 are electrically connected to acontrol terminal 31, and voltages applied to the drains of these FETs 19and 29 are supplied as control voltages for the TGs 14 and 29.

[0045] In the present VCO in a manner similar to the VCO shown in FIG.3, a series circuit comprised of the resistors 18 and the FET 19electrically connected between the output of the inverter 13 and theground voltage GND, and a series circuit comprised of the resistor 28and the FET 29 electrically connected between the output of the inverter23 and the ground potential GND are respectively operated as loads ofthe ring oscillators. Thus, when a control voltage CLT supplied to thecontrol terminal 31 rises, the channel resistances of the FETs 19 and 29decrease and hence the loads of theses ring oscillators increase,whereby oscillation frequencies are lowered.

[0046] Simultaneously, the drain voltages of the FETs 19 and 29 arereduced and the control voltages for the TGs 14 and 24 are lowered.Therefore, the TGs 14 and 24 increase in channel resistance and hence aloop delay time becomes long, whereby the oscillation frequencies of thering oscillators are further lowered. Accordingly, the present VCO canextend the control range of the oscillation frequencies as compared withthe VCO shown in FIG. 4.

[0047] Incidentally, the present invention is not limited to theabove-described embodiments. Various changes can be made thereto. Forexample, the following (a) through (g) are included as modificationsthereof.

[0048] (a) The circuit elements constituting the VCO are not limited toGaAs MESFETs.

[0049] (b) The number of the inverters constituting the ring oscillatoris not limited to the three. The number thereof may be an odd number.This number is determined according to a delay time of each inverter anda desired oscillation frequency.

[0050] (c) The configurations of the TGs 14 and 24 are not limited tothose shown in FIG. 1. Namely, such ones as to be capable of obtainingdesired conduction characteristics can be selected as the number andcharacteristics of parallel-connected transistors.

[0051] (d) When the wide frequency control range is needed in FIG. 4,the values of the resistors 18 and 28 may be set to zero. Namely, theresistors 18 and 28 may be omitted.

[0052] (e) While one ends of the FETs 19 and 29 are electricallyconnected to the ground potential GND in FIGS. 3 and 5, they might beconnected to an unillustrated source potential according to the type ofFET.

[0053] (f) The configurations of the output buffers 15 and 25 are notlimited to the illustrated ones.

[0054] (g) While the two ring oscillators are connected to each other bythe latch 32 so as to output the oscillation signals QY and QN oppositein polarity to each other, such a configuration may be set by one ringoscillator alone. In this case, the latch 32 is unnecessary.

[0055] According to the first embodiment as described above in detail,feedback resistors are respectively connected in parallel with feedbacktransistors which are connected to the outputs and inputs of invertingamplifier circuits and whose conducting states are changed by a controlvoltage. Thus, the suitable setting of the value of each resistor makesit possible to arbitrarily restrict a variable range of a conducting Xstate and set a desired oscillation frequency control range. Further, anadvantage is brought about in that when PLL is used, a synchronouspull-in time can be shortened.

[0056] According to the second embodiment, load transistors whoseconducting states are changed according to a control voltage, areconnected to the outputs of inverting amplifiers constituting ringoscillators respectively. Thus, oscillation frequencies can becontrolled without lowering the maximum values thereof.

[0057] According to the third embodiment, resistors are connected inseries with load transistors employed in a second invention. Thus, thesuitable setting of the value of each resistor makes it possible toarbitrarily restrict a variable range of load's values and set a desiredoscillation frequency control range.

[0058] While the present invention has been described with reference tothe illustrative embodiments, this description is not intended to beconstrued in a limiting sense. Various modifications of the illustrativeembodiments, as well as other embodiments of the invention, will beapparent to those skilled in the art on reference to this description.It is therefore contemplated that the appended claims will cover anysuch modifications or embodiments as fall within the true scope of theinvention.

What is claimed is:
 1. A voltage-controlled oscillator comprising: acontrol terminal applied to a control voltage; a first output terminal;a second output terminal; a first ring oscillator including an oddnumber of first inverting amplifier circuits connected in series and afirst transfer gate circuit connected between the first invertingamplifier circuits, wherein the first transfer gate circuit includes afirst transfer transistor connected between the first invertingamplifier circuits and having a control terminal connected to saidcontrol terminal, and a first resistive element connected in parallel tothe first transfer transistor; a second ring oscillator including an oddnumber of second inverting amplifier circuits,connected in series and asecond transfer gate circuit connected between the second invertingamplifier circuits, wherein the second transfer gate circuit includes asecond transfer transistor connected between the first invertingamplifier circuits and-having a control terminal connected to saidcontrol terminal, and a second resistive element connected in parallelto the second transfer transistor; a latch circuit connected to saidfirst and second ring oscillators, said latch circuit controlling saidfirst and second ring oscillators so as to output complement oscillationsignals; a first output buffer circuit having an input connected to saidfirst ring oscillator and an output connected to the first outputterminal; and a second output buffer circuit having an input connectedto said second ring oscillator and an output connected to the secondoutput terminal.
 2. A voltage-controlled oscillator according to claim1, wherein the number of the first inverting amplifier circuits is equalto the number of the second inverting amplifier circuits.
 3. Avoltage-controlled oscillator according to claim 1, wherein the firstand second transfer gate transistors are depletion type field-effecttransistors.
 4. A voltage-controlled oscillator according to claim 5,wherein the first transfer gate circuit further comprises an enhancementtype field-effect transistor connected in parallel to the first transfergate transistor, and wherein the second transfer gate circuit furthercomprises an enhancement type field-effect transistor connected inparallel to the second transfer gate transistor.
 5. A voltage-controlledoscillator according to claim 1, wherein the first and second transfergate transistors are enhancement type field-effect transistors.
 6. Avoltage-controlled oscillator according to claim 1, wherein thevoltage-controlled oscillator is composed of GaAs MESFETs.
 7. Avoltage-controlled oscillator according to claim 1, wherein each of saidfirst and second output buffer circuits includes an odd number ofinverting amplifier circuits.
 8. A voltage-controlled oscillatorcomprising: a control terminal applied to a control voltage; a firstoutput terminal; a second output terminal; a first ring oscillatorincluding an odd number of first inverting amplifier circuits connectedin series; a second ring oscillator including an odd number of secondinverting amplifier circuits connected in series; a load circuitconnected to said control terminal and said first and second ringoscillators, said load circuit applying a load to said first and secondring oscillators in response to the control voltage; a latch circuitconnected to said first and second ring oscillators, said latch circuitcontrolling said first and second ring oscillators so as to outputcomplement oscillation signals; a first output buffer circuit having aninput connected to said first ring oscillator and an output connected tothe first output terminal; and a second output buffer circuit having aninput connected to said second ring oscillator and an output connectedto the second output terminal.
 9. A voltage-controlled oscillatoraccording to claim 8, wherein the number of the first invertingamplifier circuits is equal to the number of the second invertingamplifier circuits.
 10. A voltage-controlled oscillator according toclaim 8, wherein the load circuit includes a first transistor having afirst terminal connected to receive a ground potential, a secondterminal and a control terminal connected to the control terminal, asecond transistor having a first terminal connected to receive theground potential, a second terminal and a control terminal connected tothe control terminal, a first resistive element connected between thefirst terminal of the first transistor and said first ring oscillator,and a second resistive element connected between the first terminal ofthe second transistor and said second ring oscillator.
 11. Avoltage-controlled oscillator according to claim 8, wherein thevoltage-controlled oscillator is composed of GaAs MESFETs.
 12. Avoltage-controlled oscillator according to claim 8, wherein each of saidfirst and second output buffer circuits includes an odd number ofinverting amplifier circuits.
 13. A voltage-controlled oscillatoraccording to claim 8, wherein said load circuit and said latch circuitare connected to the same nodes of said first and second ringoscillators.
 14. A voltage-controlled-oscillator comprising: a controlterminal applied to a control voltage; a first output terminal; a secondoutput terminal; a first ring oscillator including an odd number offirst inverting amplifier circuits connected in series and a firsttransfer transistor connected between the first inverting amplifiercircuit; a second ring oscillator including an odd number of secondinverting amplifier circuits connected in series and a second transfertransistor connected between the second inverting amplifier circuit; aload circuit connected to said control terminal, control terminals ofsaid first and second transfer transistors and said first and secondring oscillators, said load circuit applying a load to said first andsecond ring oscillators in response to the control voltage, said loadcircuit further applying a voltage to the first and second transfertransistors in response to the control voltage; a latch circuitconnected to said first and second ring oscillators, said latch circuitcontrolling said first and second ring oscillators so as to outputcomplement oscillation signals; a first output buffer circuit having aninput connected to said first ring oscillator and an output connected tothe first output terminal; and a second output buffer circuit having aninput connected to said second ring oscillator and an output connectedto the second output terminal;
 15. A voltage-controlled oscillatoraccording to claim 14, wherein the number of the first invertingamplifier circuits is equal to the number of the second invertingamplifier circuits.
 16. A voltage-controlled oscillator according toclaim 4, wherein the load circuit includes a first transistor having afirst terminal connected to receive a ground potential, a secondterminal connected to the control terminal of the first transfertransistor and a control terminal connected to the control terminal, asecond transistor having a first terminal connected to receive theground potential, a second terminal connected to the control terminal ofthe second transfer transistor and a control terminal connected to thecontrol terminal, a first resistive element connected between the firstterminal of the first transistor and said first ring oscillator, and asecond resistive element connected between the first terminal of thesecond transistor and said second ring oscillator.
 17. Avoltage-controlled oscillator according to claim 14, wherein thevoltage-controlled oscillator is composed of GaAs MESFETs.
 18. Avoltage-controlled oscillator according to claim 14, wherein each ofsaid first and second output buffer circuits includes an odd number ofinverting amplifier circuits.
 19. A voltage-controlled oscillatoraccording to claim 14, wherein the first and second transfer gatetransistors are depletion type field-effect transistors.